EP2S90F1020C4N

Product Summary

The EP2S90F1020C4N is a FPGA. The core of the EP2S90F1020C4N is divided into two major blocks: a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete. The EP2S90F1020C4N is enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs.

Parametrics

EP2S90F1020C4N absolute maximum ratings: (1)Supply voltage With respect to ground:-0.2V to 4.6V; (2)DC input voltage With respect to ground:-0.5V to 3.6V; (3)DC VCC or ground current:100mA; (4)DC output current, per pin:-25mA to 25mA; (5)Power dissipation:360mW; (6)Storage temperature:-65℃ to 150℃; (7)Ambient temperature:-65℃ to 135℃; (8)Junction temperature:135℃.

Features

EP2S90F1020C4N features: (1)On-chip decompression feature almost doubles the effective configuration density; (2)Standard flash die and a controller die combined into single stacked chip package; (3)Flash memory block/sector protection capability via external flash interface; (4)Compatible with Stratix series Remote System Configuration feature; (5)Supports byte-wide configuration mode fast passive parallel(FPP); 8-bit data output per DCLK cycle; (6)Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs; (7)Pin-selectable 2-ms or 100-ms power-on reset (POR) time ; (8)Multiple configuration clock sources supported (internal oscillator and external clock input pin); (9)External clock source with frequencies up to 100 MHz; (10)Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz; (11)Clock synthesis supported via user programmable divide counter; (12)Supply voltage of 3.3 V (core and I/O); (13)Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification ; (14)Supports ISP via Jam Standard Test and Programming Language (STAPL); (15)Supports JTAG boundary scan; (16)nINIT_CONF pin allows private JTAG instruction to start FPGA configuration; (17)Internal pull-up resistor on nINIT_CONF always enabled; (18)User programmable weak internal pull-up resistors on nCS and OE pins; (19)Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines; (20)Standby mode with reduced power consumption.

Diagrams