MCF5282CVM80

Product Summary

The MCF5282CVM80 is a reduced instruction set computing (RISC) microprocessor. The MCF5282CVM80 is based on the version 2 ColdFire reduced instruction set computer (RISC) core operating at a core/bus frequency up to 66 MHz. On-chip memories connected tightly to the processor core include 512 Kbytes of Flash 81, 64 Kbytes of static random access memory (SRAM) and 2 Kbytes of configurable-cache SRAM.

Parametrics

MCF5282CVM80 absolute maximum ratings: (1)Supply Voltage:-0.3V to +4.0V; (2)Clock Synthesizer Supply Voltage:-0.3V to +4.0V; (3)RAM Memory Standby Supply Voltage:-0.3V to + 4.0V; (4)Flash Memory Supply Voltage:-0.3V to +4.0V; (5)Flash Memory Program / Erase Supply Voltage:-0.3V to + 6.0V; (6)Analog Supply Voltage:-0.3V to +6.0V; (7)Analog Reference Supply Voltage:-0.3V to +6.0V; (8)Analog ESD Protection Voltage:-0.3V to +6.0V; (9)Digital Input Voltage:-0.3V to + 6.0V; (10)Analog Input Voltage:-0.3V to + 6.0V; (11)EXTAL pin voltage:0V to 3.3V; (12)XTAL pin voltage:0V to 3.3V; (13)Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 5, 6:25mA; (14)Maximum Power Supply Current:300mA; (15)Operating Temperature Range (Packaged):-40℃ to 85℃; (16)Storage Temperature Range:-65℃ to 150℃; (17)Maximum operating junction temperature:105℃; (18)ESD Target for Human Body Model:2000V.

Features

MCF5282CVM80 features: (1)Static operation; (2)32-bit address and data path on-chip; (3)66 MHz processor core and bus frequency; (4)Sixteen general-purpose 32-bit data and address registers; (5)Implements ColdFire ISA_A with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing; (6)Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms; (7)Illegal instruction decode that allows for 68K emulation support; (8)Real time trace for determining dynamic execution path; (9)Background debug mode (BDM) for in-circuit debugging; (10)Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger; (11)Fully static operation with processor sleep and whole chip stop modes; (12)Very rapid response to interrupts from the low-power sleep mode(wake-up feature); (13)Clock enable/disable for each peripheral when not used; (14)10 BaseT capability, half or full duplex; (15)100 BaseT capability, half duplex or full duplex; (16)On-chip transmit and receive FIFOs; (17)Built-in dedicated DMA controller; (18)Memory-based flexible descriptor rings; (19)Media independent interface (MII) to transceiver (PHY).

Diagrams